Huawei Quidway S9300 Configuration Manual page 204

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
Configuration Roadmap
The configuration roadmap is as follows:
1.
2.
Data Preparation
To complete the configuration, you need the following data:
l
l
Procedure
Step 1 Verify that the clock of Switch A is the primary reference clock and enable the SSM quality
level to be used in clock source selection.
# On Switch A, enable the SSM quality level to be used in clock source selection and set the
priority of the BITS0 clock to 1.
<Quidway> system-view
[Quidway] sysname Switch-A
[SwitchA] clock ql-enable
[SwitchA] clock priority 1 source 1 system
# View the clock information on Switch A, and you can see that the inner clock and system clock
provide clock signals normally.
[SwitchA] display clock priority
Reference Clock Source
---------------------------------------------------------------------
0
1
2
3
4
5
6
7
8
9
# Verify that the SSM quality level is used in clock source selection.
[SwitchA] display clock mode
QL-Enable
Freq-Check : No.
Retrieve
Hold Type
Run Mode
Bits0
Bits1
System mode: Auto select clock source 1: BITS0.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
# Verify that the system clock selects the BITS0 clock as the clock source and that the system
clock sends clock signal to the LPUs as the output clock signal.
Issue 03 (2011-12-29)
Configure the BITS0 interface of Switch A to use the BITS clock as the input primary
reference clock. (The SSM quality level of the BITS0 clock is PRC.)
Set the mode of clock source selection on Switch A, Switch B and Switch C.
Mode of clock source selection
Priorities of clock sources
Inner Clock
BITS0
BITS1
Peer Board BITS0
Peer Board BITS1
Left Frame Clock
Right Frame Clock
FSU
Peer Board FSU
System Clock
: Yes.
: Yes.
: Hold 24 hours.
: Free.
: Locked.
: Locked.
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11 Ethernet Clock Syntonization Configuration
System bits0
254 -
1 -
255 -
255 -
255 -
255 255
255 255
255 255
255 255
- 254
bits1
-
-
-
-
-
255
255
255
255
254
192