Huawei Quidway S9300 Configuration Manual page 200

Quidway S9300 Terabit Routing Switch
Configuration Guide - Device Management
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# Verify that the SSM quality level is not used in clock source selection.
[SwitchA] display clock mode
QL-Enable
Freq-Check : No.
Retrieve
Hold Type
Run Mode
Bits0
Bits1
System mode: Auto select clock source 1: BITS0.
Bits0 mode : Auto select clock source 9: System Clock.
Bits1 mode : Auto select clock source 9: System Clock.
Clock time : Free-run
# Verify that the system clock selects the BITS0 clock as the clock source and that the system
clock sends the clock signal to the LPUs as the output clock signal.
[SwitchA] display clock selection
Type
---------------------------------------------------------------------
system
bits0
bits1
Step 2 Set the mode of clock source selection on Switch B.
# On Switch B, set the priority of the clock signal that GigabitEthernet 5/0/7 sends from the right
side of the frame to 10, and set priority of the clock signal that GigabitEthernet 5/0/3 sends from
the right side of the frame to 20. Retain the default WTR time. Set the priority of the clock signal
sent from the right side of the frame to 6.
<Quidway> system-view
[Quidway] sysname SwitchB
[SwitchB] interface GigabitEthernet 5/0/7
[SwitchB-GigabitEthernet5/0/7] clock right-frame 10
[SwitchB-GigabitEthernet5/0/7] quit
[SwitchB] interface GigabitEthernet 5/0/3
[SwitchB-GigabitEthernet5/0/3] clock right-frame 20
[SwitchB-GigabitEthernet5/0/3] quit
[SwitchB] clock priority 6 source 6 system
[SwitchB] quit
# View information about the clock sources sent from the right side of the frame. You can see
that the clock source of GigabitEthernet 5/0/7 is sent to the clock board, and the clock
syntonization direction is shown by the red arrows in
[SwitchB] display clock right-frame
Interface
---------------------------------------------------------------------
GigabitEthernet5/0/3
GigabitEthernet5/0/7
# View the clock information on Switch B, and you can see that the inner clock, Right Frame
Clock, and system clock provide clock signals normally.
[SwitchB] display clock source
Issue 03 (2011-12-29)
Peer Board BITS0
Peer Board BITS1
Left Frame Clock
Right Frame Clock
FSU
Peer Board FSU
System Clock
: No.
: Yes.
: Hold 24 hours.
: Free.
: Locked.
: Locked.
NOTE
If you want to see the clock source switching result during debugging, set the WTR time to 0.
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Copyright © Huawei Technologies Co., Ltd.
11 Ethernet Clock Syntonization Configuration
255 -
255 -
255 255
255 255
255 255
255 255
- 254
Clock Source Selected
1. BITS0
9. System Clock
9. System Clock
Figure
Priority
20
10
-
-
255
255
255
255
254
11-1.
Clock Signal Selected
N
Y
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