System Architecture - Compaq AlphaServer DS20E Reference Manual

1-4 DS20E Reference Guide

System Architecture

C-chip
Probe/
Addr.
CMD/
Addr.
CPU 0
B-cache
Figure 1– 2. System Architecture
Part Number: ER-K8F6W-UA .A01 File Name: b-ch1 System Overview.doc Last Saved On: 10/4/99 1:23 PM
The system is a departmental system provided as a pedestal or rackmount and
offers Peripheral Component Interconnect (PCI) and Industry Standard
Architecture (ISA) bus options on a single system board. The system utilizes
Alpha symmetric multi-processing technology. Figure 1–2 shows the
architecture of the system.
Command, Address, and Control lines for each Memory Array
Control lines for D-chips
Probe/
CAPbus
Addr.
P-chip
CMD/
Addr.
CPU 1
(optional)
CPU
Data
Bus
B-cache
Compaq Confidential – Need to Know Required
Writer: Robert Young Project: DS20E Reference Guide Comments:
P-chip
64 bit PCI
64 bit PCI
PAD
Bus
Memory
Data
Bus
8 D-chips
1 or 2
Memory
Banks
1 or 2
Memory
Banks
PKW1400-99