Motorola MC68HC908GP32 Technical Data Manual page 98

Analog-to-Digital Converter (ADC)
Technical Data
96
Freescale Semiconductor, Inc.
Table 5-2. ADC Clock Divide Ratio
ADIV2 ADIV1
0
0
0
0
1
X = don't care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADC input clock frequency
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ADIV2 ADIV0
Analog-to-Digital Converter (ADC)
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ADIV0 ADC Clock Rate
ADC input clock ÷ 1
0 0
ADC input clock ÷ 2
0 1
ADC input clock ÷ 4
1 0
ADC input clock ÷ 8
1 1
ADC input clock ÷ 16
X X
= 1MHz
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MC68HC908GP32 MC68HC08GP32 Rev. 6
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