Motorola MC68HC908GP32 Technical Data Manual page 55

Addr. Register Name
Analog-to-Digital Status
$003C and Control Register
(ADSCR)
Analog-to-Digital Data
$003D Register
(ADR)
Analog-to-Digital Clock
$003E Register
(ADCLK)
$003F Unimplemented
SIM Break Status Register
$FE00
(SBSR)
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
$FE01
(SRSR)
SIM Upper Byte Address
$FE02 Register
(SUBAR)
SIM Break Flag Control
$FE03 Register
(SBFCR)
Interrupt Status Register 1
$FE04
(INT1)
Interrupt Status Register 2
$FE05
(INT2)
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
Bit 7 6
Read:
COCO AIEN
Write:
Reset: 0 0
Read: AD7 AD6
Write:
Reset: 0 0
Read:
ADIV2 ADIV1
Write:
Reset: 0 0
Read:
Write:
Reset:
Read:
R R
Write:
Reset:
Read: POR PIN
Write:
POR: 1 0
Read:
R R
Write:
Reset:
Read:
BCFE R
Write:
Reset: 0
Read: IF6 IF5
Write: R R
Reset: 0 0
Read: IF14 IF13
Write: R R
Reset: 0 0
= Unimplemented
Rev. 6
—
Memory Map
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5 4 3
ADCO ADCH4 ADCH3
0 1 1
AD5 AD4 AD3
0 0 0
0
ADIV0 ADICLK
0 0 0
R R R
COP ILOP ILAD
0 0 0
R R R
R R R
IF4 IF3 IF2
R R R
0 0 0
IF12 IF11 IF10
R R R
0 0 0
R = Reserved
Memory Map
Input/Output (I/O) Section
2 1 Bit 0
ADCH2 ADCH1 ADCH0
1 1 1
AD2 AD1 AD0
0 0 0
0 0 0
0 0 0
SBSW
R R
Note
0
MODRST LVI 0
0 0 0
R R R
R R R
IF1 0 0
R R R
0 0 0
IF9 IF8 IF7
R R R
0 0 0
U = Unaffected
Technical Data
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