Transmission Start Delay (Master) - Motorola MC68HC908GP32 Technical Data Manual

Serial Peripheral Interface Module (SPI)
BUS
CLOCK
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
Technical Data
314
Freescale Semiconductor, Inc.
WRITE
INITIATION DELAY
TO SPDR
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 2;
EARLIEST
2 POSSIBLE START POINTS
LATEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 8;
EARLIEST
8 POSSIBLE START POINTS
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 32;
EARLIEST
32 POSSIBLE START POINTS
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 128;
EARLIEST
128 POSSIBLE START POINTS
Figure 20-7. Transmission Start Delay (Master)
Serial Peripheral Interface Module (SPI)
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MSB BIT 6
1 2
MC68HC908GP32
BIT 5
3
LATEST
LATEST
LATEST
MC68HC08GP32 Rev. 6
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