Control, Status, And Data Registers - Motorola MC68HC908GP32 Technical Data Manual

Addr. Register Name
Port A Data Register
$0000
(PTA)
Port B Data Register
$0001
(PTB)
Port C Data Register
$0002
(PTC)
Port D Data Register
$0003
(PTD)
Data Direction Register A
$0004
(DDRA)
Data Direction Register B
$0005
(DDRB)
Data Direction Register C
$0006
(DDRC)
Data Direction Register D
$0007
(DDRD)
Port E Data Register
$0008
(PTE)
$0009 Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
Bit 7 6
Read:
PTA7 PTA6
Write:
Reset:
Read:
PTB7 PTB6
Write:
Reset:
Read: 0
PTC6
Write:
Reset:
Read:
PTD7 PTD6
Write:
Reset:
Read:
DDRA7 DDRA6
Write:
Reset: 0 0
Read:
DDRB7 DDRB6
Write:
Reset: 0 0
Read: 0
DDRC6
Write:
Reset: 0 0
Read:
DDRD7 DDRD6
Write:
Reset: 0 0
Read: 0 0
Write:
Reset:
Read:
Write:
Reset: 0 0
= Unimplemented
Rev. 6
—
Memory Map
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5 4 3
PTA5 PTA4 PTA3
Unaffected by reset
PTB5 PTB4 PTB3
Unaffected by reset
PTC5 PTC4 PTC3
Unaffected by reset
PTD5 PTD4 PTD3
Unaffected by reset
DDRA5 DDRA4 DDRA3
0 0 0
DDRB5 DDRB4 DDRB3
0 0 0
DDRC5 DDRC4 DDRC3
0 0 0
DDRD5 DDRD4 DDRD3
0 0 0
0 0 0
Unaffected by reset
0 0 0
R = Reserved
Memory Map
Input/Output (I/O) Section
2 1 Bit 0
PTA2 PTA1 PTA0
PTB2 PTB1 PTB0
PTC2 PTC1 PTC0
PTD2 PTD1 PTD0
DDRA2 DDRA1 DDRA0
0 0 0
DDRB2 DDRB1 DDRB0
0 0 0
DDRC2 DDRC1 DDRC0
0 0 0
DDRD2 DDRD1 DDRD0
0 0 0
0
PTE1 PTE0
0 0 0
U = Unaffected
Technical Data
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