Functional Description - Motorola MC68HC908GP32 Technical Data Manual

Low-Voltage Inhibit (LVI)

14.4 Functional Description

NOTE:
NOTE:
Technical Data
190
Freescale Semiconductor, Inc.
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V voltage. Clearing the LVI reset disable bit, LVIRSTD,
DD
enables the LVI module to generate a reset when V
voltage, V . Setting the LVI enable in stop mode bit, LVISTOP,
TRIPF
enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip
point bit, LVI5OR3, enables the trip point voltage, V
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip
point voltage, V , to be configured for 3-V operation. The actual trip
TRIPF
points are shown in Section 23. Electrical
After a power-on reset (POR) the LVI's default mode of operation is 3 V.
If a 5-V system is used, the user must set the LVI5OR3 bit to raise the
trip point to 5-V operation. Note that this must be done after every power-
on reset since the default will revert back to 3-V mode after each power-
on reset. If the V supply is below the 5-V mode trip voltage but above
DD
the 3-V mode trip voltage when POR is released, the part will operate
because V defaults to 3-V mode after a POR. So, in a 5-V system
TRIPF
care must be taken to ensure that V
after POR is released.
If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the V supply is not above the V
DD
MCU will immediately go into reset. The LVI in this case will hold the part
in reset until either V
DD
which will release reset or V
re-trigger the power-on reset and reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (CONFIG1). See 8.3 Functional Description
LVI's configuration bits. Once an LVI reset occurs, the MCU remains in
reset until V rises above a voltage, V
DD
exit reset. See 19.4.2.5 Low-Voltage Inhibit (LVI) Reset
the interaction between the SIM and the LVI. The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
Low-Voltage Inhibit (LVI)
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Specifications.
is above the 5-V mode trip voltage
DD
goes above the rising 5-V trip point, V
decreases to approximately 0 V which will
DD
, which causes the MCU to
TRIPR
MC68HC908GP32
falls below a
DD
, to be
TRIPF
for 5-V mode, the
TRIPR
TRIPR
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