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Timer Interface Module (TIM)
Addr.
Register Name
Timer 1 Channel 1
$0029
Register High
(T1CH1H)
Timer 1 Channel 1
$002A
Register Low
(T1CH1L)
Timer 2 Status and Control
$002B
Register
(T2SC)
Timer 2 Counter
$002C
Register High
(T2CNTH)
Timer 2 Counter
$002D
Register Low
(T2CNTL)
Timer 2 Counter Modulo
$002E
Register High
(T2MODH)
Timer 2 Counter Modulo
$002F
Register Low
(T2MODL)
Timer 2 Channel 0 Status
$0030
and Control Register
(T2SC0)
Timer 2 Channel 0
$0031
Register High
(T2CH0H)
Figure 22-2. TIM I/O Register Summary (Sheet 2 of 3)
Technical Data
346
Freescale Semiconductor, Inc.
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
Read:
TOF
TOIE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
0
0
Read:
Bit 7
6
Write:
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
1
1
Read:
Bit 7
6
Write:
Reset:
1
1
Read:
CH0F
CH0IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
= Unimplemented
Timer Interface Module (TIM)
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5
4
3
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
0
0
TSTOP
TRST
1
0
0
13
12
11
0
0
0
5
4
3
0
0
0
13
12
11
1
1
1
5
4
3
1
1
1
MS0B
MS0A
ELS0B
0
0
0
13
12
11
Indeterminate after reset
MC68HC908GP32
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
2
1
Bit 0
0
0
0
10
9
Bit 8
1
1
1
2
1
Bit 0
1
1
1
ELS0A
TOV0
CH0MAX
0
0
0
10
9
Bit 8
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
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