Introduction - Motorola MC68HC908GP32 Technical Data Manual

Input/Output (I/O) Ports

16.2 Introduction

NOTE:
Addr. Register Name
Port A Data Register
$0000
(PTA)
Port B Data Register
$0001
(PTB)
Port C Data Register
$0002
(PTC)
Port D Data Register
$0003
(PTD)
Data Direction Register A
$0004
(DDRA)
Technical Data
212
Freescale Semiconductor, Inc.
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel
ports. All I/O pins are programmable as inputs or outputs. All individual
bits within port A, port C, and port D are software configurable with pullup
devices if configured as input port bits. The pullup devices are
automatically and dynamically disabled when a port bit is switched to
output mode.
Connect any unused I/O pins to an appropriate logic level, either V
V . Although the I/O ports do not require termination for proper
SS
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Bit 7 6
Read:
PTA7 PTA6
Write:
Reset:
Read:
PTB7 PTB6
Write:
Reset:
Read: 0
PTC6
Write:
Reset:
Read:
PTD7 PTD6
Write:
Reset:
Read:
DDRA7 DDRA6
Write:
Reset: 0 0
= Unimplemented
Figure 16-1. I/O Port Register Summary
Input/Output (I/O) Ports
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5 4 3
PTA5 PTA4 PTA3
Unaffected by reset
PTB5 PTB4 PTB3
Unaffected by reset
PTC5 PTC4 PTC3
Unaffected by reset
PTD5 PTD4 PTD3
Unaffected by reset
DDRA5 DDRA4 DDRA3
0 0 0
MC68HC908GP32
or
DD
2 1 Bit 0
PTA2 PTA1 PTA0
PTB2 PTB1 PTB0
PTC2 PTC1 PTC0
PTD2 PTD1 PTD0
DDRA2 DDRA1 DDRA0
0 0 0
MC68HC08GP32 Rev. 6
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MOTOROLA