Motorola MC68HC908GP32 Technical Data Manual page 114

Clock Generator Module (CGMC)
Technical Data
112
Freescale Semiconductor, Inc.
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit (See
read-only indicator of the mode of the filter. (See
Acquisition and Tracking
• The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
Specifications
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See
Specifications
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's
lock condition changes, toggling the LOCK bit. (See
Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below
f .
BUSMAX
Clock Generator Module (CGMC)
For More Information On This Product,
Go to: www.freescale.com
7.6.2 PLL Bandwidth Control
Modes.)
7.9 Acquisition/Lock Time
for more information.)
7.9 Acquisition/Lock Time
for more information.)
MC68HC908GP32
Register.) is a
7.4.4
7.6.1 PLL
MC68HC08GP32 Rev. 6
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