Data Direction Register D - Motorola MC68HC908GP32 Technical Data Manual

Input/Output (I/O) Ports

16.6.2 Data Direction Register D

NOTE:
NOTE:
Technical Data
228
Freescale Semiconductor, Inc.
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address: $0007
Bit 7 6
Read:
DDRD7 DDRD6
Write:
Reset: 0 0
Figure 16-14. Data Direction Register D (DDRD)
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD7–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-15 shows the port D I/O logic.
For those devices packaged in a 40-pin dual in-line package, PTD6 and
PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to
configure PTD6 and PTD7 as outputs.
Input/Output (I/O) Ports
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5 4 3
DDRD5 DDRD4 DDRD3
0 0 0
MC68HC908GP32
2 1 Bit 0
DDRD2 DDRD1 DDRD0
0 0 0
MC68HC08GP32 Rev. 6
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