Swi Instruction; Interrupt Status Registers - Motorola MC68HC908GP32 Technical Data Manual

System Integration Module (SIM)

19.6.1.2 SWI Instruction

NOTE:

19.6.1.3 Interrupt Status Registers

Technical Data
292
Freescale Semiconductor, Inc.
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
The flags in the interrupt status registers identify maskable interrupt
sources. Table 19-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 19-3. Interrupt Sources
Priority Interrupt Source
Highest
SWI instruction
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
TIM2 channel 1
TIM2 overflow
SPI receiver full
SPI transmitter empty
SCI receive error
SCI transmit
ADC conversion complete
Lowest Timebase module
System Integration Module (SIM)
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Reset
IRQ pin
PLL
SCI receive
Keyboard
MC68HC908GP32
Interrupt Status
Register Flag
—
—
IF1
IF2
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
IF12
IF13
IF14
IF15
IF16
MC68HC08GP32 Rev. 6
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