I/O Registers - Motorola MC68HC908GP32 Technical Data Manual

Serial Peripheral Interface Module (SPI)

20.14 I/O Registers

20.14.1 SPI Control Register
Technical Data
328
Freescale Semiconductor, Inc.
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
• Enables the SPI module
Address: $0010
Bit 7 6
Read: DMAS
SPRIE
Write:
Reset: 0 0
= Unimplemented
Figure 20-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
Serial Peripheral Interface Module (SPI)
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5 4 3
SPMSTR CPOL CPHA
1 0 1
MC68HC908GP32
2 1 Bit 0
SPWOM SPE SPTIE
0 0 0
MC68HC08GP32 Rev. 6
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MOTOROLA