Monitor Mode Entry Timing - Motorola MC68HC908GP32 Technical Data Manual

NOTE:
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
V
DD
4096 + 32 CGMXCLK CYCLES
RST
24 BUS CYCLES
PTA7
FROM HOST
PTA0
FROM MCU
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-8. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on
reset and brought up in monitor mode to attempt another entry. After
Rev. 6
—
Monitor ROM (MON)
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256 BUS CYCLES (MINIMUM)
1
4 1
1
Monitor ROM (MON)
Security
2 4 1
Technical Data
209