Motorola MC68HC908GP32 Technical Data Manual page 162

Central Processor Unit (CPU)
Source
Operation
Form
INC opr
INCA
INCX
Increment
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X Jump
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X Jump to Subroutine
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
Load A from M
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
Load H:X from M
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
Load X from M
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX Logical Shift Left
LSL opr,X (Same as ASL)
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
Logical Shift Right
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
Move
MOV #opr,opr
MOV X+,opr
MUL Unsigned multiply
Technical Data
160
Freescale Semiconductor, Inc.
Table 10-1. Instruction Set Summary (Continued)
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
0
(M)
H:X ← (H:X) + 1 (IX+D, DIX+)
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
Description
V H I N Z C
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
↕ – – ↕ ↕ –
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
– – – – – –
– – – – – –
A ← (M) 0 – – ↕ ↕ –
H:X ← ( M:M + 1 ) 0 – – ↕ ↕ –
X ← (M) 0 – – ↕ ↕ –
↕ – – ↕ ↕ ↕
0
b7
b0
↕ – – 0 ↕ ↕
C
b7
b0
← (M)
Destination Source
0 – – ↕ ↕ –
X:A ← (X) × (A)
– 0 – – – 0 INH
MC68HC908GP32
Effect on
CCR
DIR 3C
INH 4C
INH 5C
IX1 6C
IX 7C
SP1 9E6C
DIR BC
EXT CC
IX2 DC
IX1 EC
IX FC
DIR BD
EXT CD
IX2 DD
IX1 ED
IX FD
IMM A6
DIR B6
EXT C6
IX2 D6
IX1 E6
IX F6
SP1 9EE6
SP2 9ED6
IMM 45
DIR 55
IMM AE
DIR BE
EXT CE
IX2 DE
IX1 EE
IX FE
SP1 9EEE
SP2 9EDE
DIR 38
INH 48
INH 58
IX1 68
IX 78
SP1 9E68
DIR 34
INH 44
INH 54
IX1 64
IX 74
SP1 9E64
DD 4E
DIX+ 5E
IMD 6E
IX+D 7E
42
MC68HC08GP32
•
MOTOROLA
dd 4
1
1
ff 4
3
ff 5
dd 2
hh ll 3
ee ff 4
ff 3
2
dd 4
hh ll 5
ee ff 6
ff 5
4
ii 2
dd 3
hh ll 4
ee ff 4
ff 3
2
ff 4
ee ff 5
ii jj 3
dd 4
ii 2
dd 3
hh ll 4
ee ff 4
ff 3
2
ff 4
ee ff 5
dd 4
1
1
ff 4
3
ff 5
dd 4
1
1
ff 4
3
ff 5
dd dd 5
dd 4
ii dd 4
dd 4
5
Rev. 6
—