Transmission Format (Cpha = 0) - Motorola MC68HC908GP32 Technical Data Manual

SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
MISO/MOSI
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
1 2
MSB BIT 6
MSB BIT 6
Figure 20-4. Transmission Format (CPHA = 0)
BYTE 1
Figure 20-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
Rev. 6
—
Serial Peripheral Interface Module (SPI)
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Serial Peripheral Interface Module (SPI)
3 4 5 6
BIT 5 BIT 4 BIT 3 BIT 2
BIT 5 BIT 4 BIT 3 BIT 2
BYTE 2
Transmission Formats
7 8
BIT 1 LSB
BIT 1 LSB
BYTE 3
Technical Data
311