Motorola MC68HC908GP32 Technical Data Manual page 387

SS
INPUT
SPSCK OUTPUT
NOTE
CPOL = 0
SPSCK OUTPUT
NOTE
CPOL = 1
MISO
INPUT
MOSI
OUTPUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
SS
INPUT
SPSCK OUTPUT
CPOL = 0
SPSCK OUTPUT
CPOL = 1
MISO
INPUT
10
MOSI
OUTPUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
SS PIN OF MASTER HELD HIGH
4
5
MSB IN
11
MASTER MSB OUT
a) SPI Master Timing (CPHA = 0)
SS PIN OF MASTER HELD HIGH
1
5
4
5
4
MSB IN
11
MASTER MSB OUT
b) SPI Master Timing (CPHA = 1)
Figure 23-16. SPI Master Timing
Rev. 6
—
Electrical Specifications
For More Information On This Product,
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1
5
4
BITS 6–1
10
BITS 6–1
BITS 6–1
10
BITS 6–1
Electrical Specifications
3.0-V SPI Characteristics
6 7
LSB IN
11
MASTER LSB OUT
NOTE
NOTE
6 7
LSB IN
MASTER LSB OUT
Technical Data
385