Motorola MC68HC908GP32 Technical Data Manual page 359

NOTE:
NOTE:
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as
PS[2:0] bits.
Table 22-2. Prescaler Selection
PS2 PS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Rev. 6
—
Timer Interface Module (TIM)
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Go to: www.freescale.com
Table 22-2 shows. Reset clears the
PS0 TIM Clock Source
Internal bus clock ÷ 1
0
Internal bus clock ÷ 2
1
Internal bus clock ÷ 4
0
Internal bus clock ÷ 8
1
Internal bus clock ÷ 16
0
Internal bus clock ÷ 32
1
Internal bus clock ÷ 64
0
1
Timer Interface Module (TIM)
I/O Registers
Not available
Technical Data
357