Irq Status And Control Register (Intscr) - Motorola MC68HC908GP32 Technical Data Manual

External Interrupt (IRQ)
Technical Data
180
Freescale Semiconductor, Inc.
Address: $001D
Bit 7 6
Read:
Write:
Reset: 0 0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
External Interrupt (IRQ)
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5 4 3
IRQF
0 0 0
MC68HC908GP32
2 1 Bit 0
0
IMASK MODE
ACK
0 0 0
MC68HC08GP32 Rev. 6
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