Table of Contents
Advertisement
Memory Map
Addr.
Register Name
Configuration Register 2
$001E
(CONFIG2)†
Configuration Register 1
$001F
(CONFIG1)
Timer 1 Status and Control
$0020
Register
(T1SC)
Timer 1 Counter
$0021
Register High
(T1CNTH)
Timer 1 Counter
$0022
Register Low
(T1CNTL)
Timer 1 Counter Modulo
$0023
Register High
(T1MODH)
Timer 1 Counter Modulo
$0024
Register Low
(T1MODL)
Timer 1 Channel 0 Status
$0025
and Control Register
(T1SC0)
Timer 1 Channel 0
$0026
Register High
(T1CH0H)
Timer 1 Channel 0
$0027
Register Low
(T1CH0L)
† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Technical Data
50
Freescale Semiconductor, Inc.
Bit 7
6
Read:
0
0
Write:
Reset:
0
0
Read:
COPRS
LVISTOP LVIRSTD LVIPWRD LVI5OR3
Write:
†
Reset:
0
0
Read:
TOF
TOIE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
0
0
Read:
Bit 7
6
Write:
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
1
1
Read:
Bit 7
6
Write:
Reset:
1
1
Read:
CH0F
CH0IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
Read:
Bit 7
6
Write:
Reset:
= Unimplemented
Memory Map
For More Information On This Product,
Go to: www.freescale.com
5
4
3
0
0
0
0
0
0
0
0
0
0
0
TSTOP
TRST
1
0
0
13
12
11
0
0
0
5
4
3
0
0
0
13
12
11
1
1
1
5
4
3
1
1
1
MS0B
MS0A
ELS0B
0
0
0
13
12
11
Indeterminate after reset
5
4
3
Indeterminate after reset
R = Reserved
MC68HC908GP32
2
1
Bit 0
0
OSC-
SCIBD-
STOPENB
SRC
0
0
0
†
SSREC
STOP
COPD
0
0
0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
2
1
Bit 0
0
0
0
10
9
Bit 8
1
1
1
2
1
Bit 0
1
1
1
ELS0A
TOV0
CH0MAX
0
0
0
10
9
Bit 8
2
1
Bit 0
U = Unaffected
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
Advertisement
Chapters
Table of Contents
