System Integration Module (SIM)
19.2 Introduction
Technical Data
278
Freescale Semiconductor, Inc.
19.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
19.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
19.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
19.8.1
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 298
19.8.2
SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 300
19.8.3
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 301
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in
Figure
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
Master reset control, including power-on reset (POR) and COP
timeout
•
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
Table 19-1
shows the internal signal names used in this section.
System Integration Module (SIM)
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19-1.
Table 19-1
is a summary of the SIM
MC68HC908GP32
MC68HC08GP32
Rev. 6
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MOTOROLA