Sim Counter During Stop Mode Recovery; Sim Counter And Reset States; Exception Control; Interrupts - Motorola MC68HC908GP32 Technical Data Manual

System Integration Module (SIM)

19.5.2 SIM Counter During Stop Mode Recovery

19.5.3 SIM Counter and Reset States

19.6 Exception Control

19.6.1 Interrupts

Technical Data
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Freescale Semiconductor, Inc.
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
External reset has no effect on the SIM counter.
for details.) The SIM counter is free-running after all reset states.
19.4.2 Active Resets from Internal Sources
internal reset recovery sequences.)
Normal, sequential program execution can be changed in three different
ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
System Integration Module (SIM)
For More Information On This Product,
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(See 19.7.2 Stop Mode
for counter control and
MC68HC908GP32 MC68HC08GP32
•
(See
Rev. 6
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