Monitor Mode Circuit - Motorola MC68HC908GP32 Technical Data Manual

1
+
10 µ F
3
4
10 µ F
+
2
DB-25
2 5
3 6
7
Notes:
1. For monitor mode entry when IRQ = V
SW1: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
SW1: Position B — Bus clock = CGMXCLK ÷ 2
2. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator.
SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL.
3. See Table 15-1
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
6–30 pF
20
MC145407
+
10 µ F
18
32.768 kHz XTAL
17
+
V
10 µ F
DD
19
16
15
1
2
6
4
7
TST
for IRQ voltage level requirements.
Figure 15-1. Monitor Mode Circuit
Rev. 6
—
Monitor ROM (MON)
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0.1 µ F
V
TST
(SEE NOTE 3)
10 k Ω
(SEE NOTES 2
AND 3)
C
SW2
D
10 k
0.033 µ F
SW3
C
(SEE NOTE 2)
D
SW4
C
(SEE NOTE 2)
330 k Ω
D
6–30 pF
0.1 µ F
V
DD
14
MC74HC125
10 k Ω
3
5
V
DD
A
SW1
(SEE NOTE 1)
B
:
Monitor ROM (MON)
Functional Description
68HC908GP32
RST
RESET VECTORS
$FFFE
$FFFF
IRQ
V
DD
V
DDA
CGMXFC
OSC1
OSC2
PTA7
V
SS
V
SSAD
V
SSA
V
DD
V
DD
V
DDAD
V
DD
PTA0
PTC3
V
DD
PTC0
PTC1
Technical Data
197