Sci Status Register 2 - Motorola MC68HC908GP32 Technical Data Manual

Table of Contents

Advertisement

Serial Communications Interface Module (SCI)

18.9.5 SCI Status Register 2

Technical Data
272
Freescale Semiconductor, Inc.
SCI status register 2 contains flags to signal the following conditions:
Break character detected
Incoming data
Address:
$0017
Bit 7
6
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 18-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
Serial Communications Interface Module (SCI)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
0
0
0
MC68HC908GP32
2
1
Bit 0
BKF
RPF
0
0
0
MC68HC08GP32
Rev. 6
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents