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Timer Interface Module (TIM)
22.10.4 TIM Channel Status and Control Registers
Technical Data
360
Freescale Semiconductor, Inc.
Each of the TIM channel status and control registers:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 0% and 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
6
Read:
CH0F
CH0IE
Write:
0
Reset:
0
0
Figure 22-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
6
Read:
CH1F
CH1IE
Write:
0
Reset:
0
0
= Unimplemented
Figure 22-10. TIM Channel 1 Status and Control Register (TSC1)
Timer Interface Module (TIM)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
MS0B
MS0A
ELS0B
0
0
0
5
4
3
0
MS1A
ELS1B
0
0
0
MC68HC908GP32
2
1
Bit 0
ELS0A
TOV0
CH0MAX
0
0
0
2
1
Bit 0
ELS1A
TOV1
CH1MAX
0
0
0
MC68HC08GP32
Rev. 6
•
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