Motorola MC68HC908GP32 Technical Data Manual page 29

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
Figure
20-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 311
20-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
20-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 312
20-7 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 314
20-8 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 315
20-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 317
20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 318
20-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 321
20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 328
20-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .330
20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
21-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
21-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . . 337
22-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
22-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 350
22-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 356
22-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 358
22-6 TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 358
22-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .359
22-8 TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 359
22-9 TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 360
22-10 TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 360
22-11 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
22-12 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 364
22-13 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 364
22-14 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 364
22-15 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 364
23-1 Typical High-Side Driver Characteristics -
Port PTA7-PTA0 (V
23-2 Typical High-Side Driver Characteristics -
Port PTA7-PTA0 (V
23-3 Typical High-Side Driver Characteristics -
Port PTC4-PTC0 (V
Rev. 6
-
List of Figures
For More Information On This Product,
Go to: www.freescale.com
Title
= 4.5 Vdc) . . . . . . . . . . . . . . . . . . . 374
DD
= 2.7 Vdc) . . . . . . . . . . . . . . . . . . . 374
DD
= 4.5 Vdc) . . . . . . . . . . . . . . . . . . 375
DD
List of Figures
Page
Technical Data
27