Motorola MC68HC908GP32 Technical Data Manual page 118

Clock Generator Module (CGMC)
NOTE:
Technical Data
116
Freescale Semiconductor, Inc.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program
the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program
the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
d. In the PLL VCO range select register (PMRS), program the
binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program
the binary coded equivalent of R.
The values for P, E, N, L, and R can only be programmed when the PLL
is off (PLLON = 0).
Table 7-1 provides numeric examples (numbers are in hexadecimal
notation):
Table 7-1. Numeric Example
f
BUS
2.0 MHz
2.4576 MHz
2.5 MHz
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
Clock Generator Module (CGMC)
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f
R
RCLK
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
32.768 kHz 1
MC68HC908GP32
N P E L
F5 0 0 D1
12C 0 1 80
132 0 1 83
1E9 0 1 D1
258 0 2 80
263 0 2 82
384 0 2 C0
3D1 0 2 D0
MC68HC08GP32 Rev. 6
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