Cgmc I/O Register Summary - Motorola MC68HC908GP32 Technical Data Manual

Clock Generator Module (CGMC)
Addr. Register Name
PLL Control Register
$0036
(PCTL)
PLL Bandwidth Control
$0037 Register
(PBWC)
PLL Multiplier Select High
$0038 Register
(PMSH)
PLL Multiplier Select Low
$0039 Register
(PMSL)
PLL VCO Range Select
$003A Register
(PMRS)
PLL Reference Divider
$003B Select Register
(PMDS)
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Technical Data
122
Freescale Semiconductor, Inc.
• PLL VCO range select register (PMRS)
(See 7.6.5 PLL VCO Range Select
• PLL reference divider select register (PMDS)
(See 7.6.6 PLL Reference Divider Select
Figure 7-3 is a summary of the CGMC registers.
Bit 7 6
Read: PLLF
PLLIE
Write:
Reset: 0 0
Read: LOCK
AUTO
Write:
Reset: 0 0
Read: 0 0
Write:
Reset: 0 0
Read:
MUL7 MUL6
Write:
Reset: 0 1
Read:
VRS7 VRS6
Write:
Reset: 0 1
Read: 0 0
Write:
Reset: 0 0
= Unimplemented
Figure 7-3. CGMC I/O Register Summary
Clock Generator Module (CGMC)
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Register.)
5 4 3
PLLON BCS PRE1
1 0 0
0 0
ACQ
0 0 0
0 0
MUL11
0 0 0
MUL5 MUL4 MUL3
0 0 0
VRS5 VRS4 VRS3
0 0 0
0 0
RDS3
0 0 0
R = Reserved
MC68HC908GP32
Register.)
2 1 Bit 0
PRE0 VPR1 VPR0
0 0 0
0 0
R
0 0 0
MUL10 MUL9 MUL8
0 0 0
MUL2 MUL1 MUL0
0 0 0
VRS2 VRS1 VRS0
0 0 0
RDS2 RDS1 RDS0
0 0 1
MC68HC08GP32 Rev. 6
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MOTOROLA