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Resets and Interrupts
4.4.2.8 SCI
Technical Data
82
Freescale Semiconductor, Inc.
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Overflow bit (OVRF) — The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.
SCI CPU interrupt sources:
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SCI transmitter empty bit (SCTE) — SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.
•
Transmission complete bit (TC) — TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.
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SCI receiver full bit (SCRF) — SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.
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Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
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Receiver overrun bit (OR) — OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.
Resets and Interrupts
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MC68HC908GP32
MC68HC08GP32
•
Rev. 6
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MOTOROLA
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