Port A I/O Circuit - Motorola MC68HC908GP32 Technical Data Manual

PTAPUE Bit DDRA Bit
1 0
0 0
X 1
NOTES:
1. X = Don't care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
PTAPUEx
READ PTA ($0000)
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
the operation of the port A pins.
Table 16-2. Port A Pin Functions
PTA Bit I/O Pin Mode
(1)
Input, V
X
DD
X
Input, Hi-Z
X Output
by internal pullup device
DD
Rev. 6
—
Input/Output (I/O) Ports
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DDRAx
RESET
PTAx
V
DD
INTERNAL
PULLUP
DEVICE
Figure 16-4. Port A I/O Circuit
Accesses
to DDRA
Read/Write
(4)
DDRA7–DDRA0
(2)
DDRA7–DDRA0
DDRA7–DDRA0
Input/Output (I/O) Ports
Table 16-2 summarizes
Accesses to PTA
Read Write
Pin
PTA7–PTA0
Pin
PTA7–PTA0
PTA7–PTA0 PTA7–PTA0
Technical Data
Port A
PTAx
(3)
(3)
217