Sim Break Status Register (Sbsr); Break Status Register - Motorola MC68HC908GP32 Technical Data Manual

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6.6.3 Break Status Register

HIBYTE
LOBYTE
;
DOLO
RETURN
MC68HC908GP32
MC68HC08GP32
MOTOROLA
Freescale Semiconductor, Inc.
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop or wait mode. The flag is useful in
applications requiring a return to stop or wait mode after exiting from a
break interrupt.
Address:
$FE00
Bit 7
6
Read:
R
R
Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Figure 6-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This read/write bit is set when a break interrupt causes an exit from
stop or wait mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Break interrupt during stop/wait mode
0 = No break interrupt during stop/wait mode
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting 1 from it. The
following code is an example.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
EQU
5
EQU
6
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
TST
LOBYTE,SP
BNE
DOLO
DEC
HIBYTE,SP
DEC
LOBYTE,SP
PULH
RTI
Rev. 6
Break Module (BRK)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
R
R
R
R
= Reserved
;
See if wait mode or stop mode
;
was exited by break.
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
Break Module (BRK)
Break Module Registers
2
1
Bit 0
SBSW
R
R
Note
0
Technical Data
103

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