Pll Multiplier Select Register Low - Motorola MC68HC908GP32 Technical Data Manual

Clock Generator Module (CGMC)

7.6.4 PLL Multiplier Select Register Low

NOTE:
Technical Data
128
Freescale Semiconductor, Inc.
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address: $0038
Bit 7 6
Read:
MUL7 MUL6
Write:
Reset: 0 1
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See
Circuits and 7.4.6 Programming the
written when the PLLON bit in the PCTL is set. A value of $0000 in the
multiplier select registers configures the modulo feedback divider the
same as a value of $0001. Reset initializes the register to $40 for a
default multiply value of 64.
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
Clock Generator Module (CGMC)
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5 4 3
MUL5 MUL4 MUL3
0 0 0
PLL.) MUL7–MUL0 cannot be
MC68HC908GP32
2 1 Bit 0
MUL2 MUL1 MUL0
0 0 0
7.4.3 PLL
MC68HC08GP32 Rev. 6
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