Pll Reference Divider Select Register - Motorola MC68HC908GP32 Technical Data Manual

Clock Generator Module (CGMC)

7.6.6 PLL Reference Divider Select Register

NOTE:
NOTE:
NOTE:
Technical Data
130
Freescale Semiconductor, Inc.
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
Address: $003B
Bit 7 6
Read: 0 0
Write:
Reset: 0 0
= Unimplemented
Figure 7-9. PLL Reference Divider Select Register (PMDS)
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See
Programming the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See 7.4.7 Special Programming
initializes the register to $01 for a default divide value of 1.
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
Clock Generator Module (CGMC)
For More Information On This Product,
Go to: www.freescale.com
5 4 3
0 0
RDS3
0 0 0
7.4.3 PLL Circuits
PLL.) RDS7–RDS0 cannot be written when the
Exceptions.) Reset
MC68HC908GP32
2 1 Bit 0
RDS2 RDS1 RDS0
0 0 1
and 7.4.6
MC68HC08GP32 Rev. 6
• —
MOTOROLA