Lvi Status Register - Motorola MC68HC908GP32 Technical Data Manual

14.5 LVI Status Register

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
The LVI status register (LVISR) indicates if the V
detected below the V
Address: $FE0C
Bit 7 6
Read: LVIOUT 0
Write:
Reset: 0 0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
V trip voltage. (See
TRIPF
Table 14-1. LVIOUT Bit Indication
V
DD
V
DD
V
TRIPF
Rev. 6
—
Low-Voltage Inhibit (LVI)
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level.
TRIPF
5 4
0 0
0 0
Table 14-1.) Reset clears the LVIOUT bit.
V
DD
> V
TRIPR
< V
TRIPF
< V < V
Previous value
DD TRIPR
Low-Voltage Inhibit (LVI)
LVI Status Register
voltage was
DD
3 2 1
0 0 0
0 0 0
voltage falls below the
DD
LVIOUT
0
1
Technical Data
Bit 0
0
0
193