Motorola MC68HC908GP32 Technical Data Manual page 70

Low-Power Modes
NOTE:
Technical Data
68
Freescale Semiconductor, Inc.
• Timebase module (TBM) interrupt — A TBM interrupt loads the
program counter with the contents of locations $FFDC and $FFDD
when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an
oscillator stabilization delay. A 12-bit stop recovery counter inhibits the
system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register
controls the oscillator stabilization delay during stop recovery. Setting
SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
Low-Power Modes
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MC68HC908GP32 MC68HC08GP32
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Rev. 6
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MOTOROLA