Tim Channel Registers - Motorola MC68HC908GP32 Technical Data Manual

NOTE:
NOTE:

22.10.5 TIM Channel Registers

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 22-11 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
CHxMAX
Figure 22-11. CHxMAX Latency
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
Rev. 6
—
Timer Interface Module (TIM)
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Timer Interface Module (TIM)
OVERFLOW OVERFLOW
OUTPUT OUTPUT
COMPARE COMPARE
I/O Registers
OVERFLOW
OUTPUT
COMPARE
Technical Data
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