Motorola MC68HC908GP32 Technical Data Manual page 229

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input
capture/output compare pins. The edge/level select bits, ELSxB and
ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are
timer channel I/O pins or general-purpose I/O pins.
Timer Interface Module
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module.
When the SPE bit is clear, the PTD3/SPSCK pin is available for
general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTD2/MOSI pin is available
for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the SPI module. However, the
DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTD0/SS pin is available for general-purpose I/O. When the SPI is
enabled, the DDRB0 bit in data direction register B (DDRB) has no
effect on the PTD0/SS pin.
Rev. 6
—
Input/Output (I/O) Ports
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(TIM).
Input/Output (I/O) Ports
Port D
See Section 22.
Table 16-5.
Technical Data
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