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Timer Interface Module (TIM)
22.10.2 TIM Counter Registers
NOTE:
Technical Data
358
Freescale Semiconductor, Inc.
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
0
0
= Unimplemented
Figure 22-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
0
0
= Unimplemented
Figure 22-6. TIM Counter Registers Low (TCNTL)
Timer Interface Module (TIM)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
13
12
11
0
0
0
5
4
3
5
4
3
0
0
0
MC68HC908GP32
2
1
Bit 0
10
9
Bit 8
0
0
0
2
1
Bit 0
2
1
Bit 0
0
0
0
MC68HC08GP32
Rev. 6
•
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MOTOROLA
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