Motorola MC68HC908GP32 Technical Data Manual page 164

Central Processor Unit (CPU)
Source
Operation
Form
SBC #opr
SBC opr
SBC opr
SBC opr,X
Subtract with Carry
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC Set Carry Bit
SEI Set Interrupt Mask
STA opr
STA opr
STA opr,X
STA opr,X Store A in M
STA ,X
STA opr,SP
STA opr,SP
STHX opr Store H:X in M
STOP Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X Store X in M
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
Subtract
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI Software Interrupt
TAP Transfer A to CCR
TAX Transfer A to X
TPA Transfer CCR to A
Technical Data
162
Freescale Semiconductor, Inc.
Table 10-1. Instruction Set Summary (Continued)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Central Processor Unit (CPU)
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Description
V H I N Z C
A ← (A) – (M) – (C) ↕ – – ↕ ↕ ↕
C ← 1
I ← 1
M ← (A)
(M:M + 1) ← (H:X)
I ← 0; Stop Oscillator
M ← (X)
A ← (A) – (M) ↕ – – ↕ ↕ ↕
SP ← (SP) – 1; I ← 1
CCR ← (A) ↕ ↕ ↕ ↕ ↕ ↕ INH
X ← (A)
A ← (CCR)
MC68HC908GP32
Effect on
CCR
IMM A2
DIR B2
EXT C2
IX2 D2
IX1 E2
IX F2
SP1 9EE2
SP2 9ED2
– – – – – 1 INH 99
– – 1 – – – INH 9B
DIR B7
EXT C7
IX2 D7
0 – – ↕ ↕ –
IX1 E7
IX F7
SP1 9EE7
SP2 9ED7
0 – – ↕ ↕ – DIR
35
– – 0 – – – INH 8E
DIR BF
EXT CF
IX2 DF
0 – – ↕ ↕ –
IX1 EF
IX FF
SP1 9EEF
SP2 9EDF
IMM A0
DIR B0
EXT C0
IX2 D0
IX1 E0
IX F0
SP1 9EE0
SP2 9ED0
– – 1 – – – INH 83
84
– – – – – – INH 97
– – – – – – INH 85
MC68HC08GP32
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MOTOROLA
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