Data Direction Register C - Motorola MC68HC908GP32 Technical Data Manual

16.5.2 Data Direction Register C

NOTE:
NOTE:
MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
Data direction register C (DDRC) determines whether each port C pin is
an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address: $0006
Bit 7 6
Read: 0
DDRC6
Write:
Reset: 0 0
= Unimplemented
Figure 16-10. Data Direction Register C (DDRC)
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC6–DDRC0, configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 16-11 shows the port C I/O logic.
For those devices packaged in a 40-pin dual in-line package and 42-pin
shrink dual in-line package, PTC5 and PTC6 are connected to ground
internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5
and PTC6 as inputs.
Rev. 6
—
Input/Output (I/O) Ports
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5 4 3
DDRC5 DDRC4 DDRC3
0 0 0
Input/Output (I/O) Ports
Port C
2 1 Bit 0
DDRC2 DDRC1 DDRC0
0 0 0
Technical Data
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