Sci Control Register 2 - Motorola MC68HC908GP32 Technical Data Manual

Serial Communications Interface Module (SCI)
NOTE:

18.9.2 SCI Control Register 2

Technical Data
262
Freescale Semiconductor, Inc.
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity.
bit.
1 = Odd parity
0 = Even parity
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 18-5. Character Format Selection
Control Bits
PEN and
M
PTY
0 0X
1 0X
0 10
0 11
1 10
1 11
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
Serial Communications Interface Module (SCI)
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(See Table 18-5.) Reset clears the PTY
Character Format
Start Data
Parity
Bits Bits
1 8 None
1 9 None
1 7 Even
1 7 Odd
1 8 Even
1 8 Odd
MC68HC908GP32
Stop Character
Bits Length
1 10 bits
1 11 bits
1 10 bits
1 10 bits
1 11 bits
1 11 bits
MC68HC08GP32 Rev. 6
• —
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