Adc Data Register (Adr); Adc Clock Register (Adclk); Adc Data Register; Adc Clock Register - Motorola MC68HC908GP32 Technical Data Manual

5.8.2 ADC Data Register

5.8.3 ADC Clock Register

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address: $003D
Bit 7 6
Read: AD7 AD6
Write:
Reset: 0 0
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
Address: $003E
Bit 7 6
Read:
ADIV2 ADIV1
Write:
Reset: 0 0
= Unimplemented
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock.
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Rev. 6
—
Analog-to-Digital Converter (ADC)
For More Information On This Product,
Go to: www.freescale.com
Analog-to-Digital Converter (ADC)
5 4 3
AD5 AD4 AD3
0 0 0
5 4 3
0
ADIV0 ADICLK
0 0 0
I/O Registers
2 1 Bit 0
AD2 AD1 AD0
0 0 0
2 1 Bit 0
0 0 0
0 0 0
Table 5-2 shows the
Technical Data
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