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7.4.7 Special Programming Exceptions
7.4.8 Base Clock Selector Circuit
MC68HC908GP32
MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
The programming method described in
does not account for three possible exceptions. A value of 0 for R, N, or
L is meaningless when used in the equations given. To account for these
exceptions:
•
A 0 value for R or N is interpreted exactly the same as a value of 1.
•
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See
7.4.8 Base Clock Selector
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
Rev. 6
—
Clock Generator Module (CGMC)
For More Information On This Product,
Go to: www.freescale.com
Clock Generator Module (CGMC)
Functional Description
7.4.6 Programming the PLL
Circuit.)
Technical Data
117
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