Resets and Interrupts
4.3.3.1 Power-On Reset
Technical Data
72
Freescale Semiconductor, Inc.
A power-on reset (POR) is an internal reset caused by a positive
transition on the V
DD
reset the MCU. This distinguishes between a reset and a POR. The POR
is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
•
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
•
Drives the RST pin low during the oscillator stabilization delay
•
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
•
Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay
•
Sets the POR and LP bits in the SIM reset status register and
clears all other bits in the register
OSC1
(1)
PORRST
CYCLES
CGMXCLK
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
Resets and Interrupts
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pin. V
at the POR must go completely to 0 V to
DD
4096
32
32
CYCLES
CYCLES
MC68HC908GP32
MC68HC08GP32
Rev. 6
•
—
MOTOROLA