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Timer Interface Module (TIM)
22.10.1 TIM Status and Control Register
Technical Data
356
Freescale Semiconductor, Inc.
The TIM status and control register (TSC):
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
6
Read:
TOF
TOIE
Write:
0
Reset:
0
0
= Unimplemented
Figure 22-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a
logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
Timer Interface Module (TIM)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
0
0
TSTOP
TRST
1
0
0
MC68HC908GP32
2
1
Bit 0
PS2
PS1
PS0
0
0
0
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
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