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MC68HC08GP32
A.6 Reserved Registers
A.7 Monitor ROM
Technical Data
402
Freescale Semiconductor, Inc.
Address:
$001E
Bit 7
6
Read:
0
0
Write:
Reset:
Figure A-3. Mask Option Register 2 (MOR2)
Address:
$001F
Bit 7
6
Read: COPRS
LVISTOP LVIRSTD LVIPWRD LVI5OR3
Write:
Reset:
Figure A-4. Mask Option Register 1 (MOR1)
The bit functions for these two registers are the same as the
configuration registers in MC68HC908GP32 (see
Configuration Register
The two registers at $FE08 and $FF7E are reserved locations on the
MC68HC08GP32.
On the MC68HC908GP32, these two locations are the FLASH control
register and the FLASH block protect register respectively.
The monitor program (monitor ROM, $FE20–$FF52) on the
MC68HC08GP32 is for device testing only.
The monitor mode entry by blank reset vector bit, MODRST bit (bit 2 at
$FE01), is not used in the ROM device — the reset vector will always
contain data in the MC68HC08GP32.
MC68HC08GP32
For More Information On This Product,
Go to: www.freescale.com
5
4
3
0
0
0
Mask defined
5
4
3
Mask defined
(CONFIG)).
MC68HC908GP32
2
1
Bit 0
OSC-
SCIBD-
0
STOPENB
SRC
2
1
Bit 0
SSREC
STOP
COPD
Section 8.
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
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