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System Integration Module (SIM)
Interrupt Status
Register 3
19.6.2 Reset
19.6.3 Break Interrupts
Technical Data
294
Freescale Semiconductor, Inc.
Address:
$FE06
Bit 7
6
Read:
0
0
Write:
R
R
Reset:
0
0
R
= Reserved
Figure 19-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the
source shown in
Table
1 = Interrupt request present
0 = No interrupt request present
All reset sources always have equal and highest priority and cannot be
arbitrated.
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output.
Section 22. Timer Interface Module
the break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
5
4
3
0
0
0
R
R
R
0
0
0
19-3.
(TIM).) The SIM puts the CPU into
MC68HC908GP32
2
1
Bit 0
0
IF16
IF15
R
R
R
0
0
0
(See
MC68HC08GP32
Rev. 6
•
—
MOTOROLA
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