Cop Reset; Low-Voltage Inhibit Reset; Illegal Opcode Reset - Motorola MC68HC908GP32 Technical Data Manual

4.3.3.2 COP Reset

4.3.3.3 Low-Voltage Inhibit Reset

4.3.3.4 Illegal Opcode Reset

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI
• Drives the RST pin low for as long as V
voltage and during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
• Sets the LVI bit in the SIM reset status register
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
Rev. 6
—
Resets and Interrupts
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Resets and Interrupts
voltage.
tripf
voltage
tripr
is below the LVI
DD
Resets
tripr
Technical Data
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