Motorola MC68HC908GP32 Technical Data Manual page 141

MC68HC908GP32 MC68HC08GP32
•
MOTOROLA
Freescale Semiconductor, Inc.
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
Section 9. Computer Operating Properly
1 = COP timeout period = 2
0 = COP timeout period = 2
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
3.6.2 Stop Mode.)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
Section 14. Low-Voltage Inhibit
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module.
Section 14. Low-Voltage Inhibit
for the LVI should match the operating V
Electrical Specifications
the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
Rev. 6
—
Configuration Register (CONFIG)
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Configuration Register (CONFIG)
(COP).)
13 4
– 2 CGMXCLK cycles
18 4
– 2 CGMXCLK cycles
(LVI).)
(See Section 14. Low-Voltage
(LVI).) The voltage mode selected
. See Section 23.
DD
for the LVI's voltage trip points for each of
Functional Description
(See
(See
(See
Technical Data
139